VeriSilicon GSMC 0.25um 2.5V/3.3V PCI I/O Cell Library developed by VeriSilicon is optimized for Grace Semiconductor Manufacturing Corporation (GSMC) 0.25um logic 1P5M 2.5V/3.3V process. This library can take 5V tolerance. This library supports both Stagger I/O pads and Inline I/O pads.
- Process:SMIC 55nm Low Power Process
- SMIC 55nm 1.2V/2.5V Low Leakage 1P8M 2TM
- Compliant with the MIPI D-PHY spec v1.1
- Data rate per lane: High-Speed mode 80M~1.5Gbps, Low-Power mode 10Mbps
- Lane number: 1 clock + 4 data
- On-chip differential 100Ω terminations with calibration