MIPI C-PHY v1.0 D-PHY v1.2 RX 2 trios/2 Lanes in TSMC (12nm, N5)
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SMIC 130nm G SSTL2
特色
- SMIC 0.13um Logic 1P8M Salicide1.2V/3.3V Process
- Suitable for 6,7 and 8 layers application
- Pad opening window size:62um * 62um
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