USB 3.2 Gen2/Gen1 PHY IP in TSMC(5nm, 6nm, 7nm,12nm/16nm, 22nm, 28nm, 40nm, 55nm)
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SMIC 130nm G SSTL2 IO
特色
- SMIC 0.13um Logic 1P8M Salicide 1.2V/3.3V Process;
- Suitable for 6,7 and 8 layers application;
- SSTL2 IO compatible with SP013D3W
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