MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, N7, N5A)
SMIC 130nm G LVDS 1.25Gbps Receiver
特色
- SMIC 0.13um 1.2V/3.3VLogic Process;
- Same height (200um) as SMIC 0.13um Standard IO Library sets;
- Suitable for 6,7 and 8 layers application(4)1.25Gbps
查看 SMIC 130nm G LVDS 1.25Gbps Receiver 详细介绍:
- 查看 SMIC 130nm G LVDS 1.25Gbps Receiver 完整数据手册
- 联系 SMIC 130nm G LVDS 1.25Gbps Receiver 供应商