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SMIC 0.18um LVDS Transceiver/Receiver
This transmitter provides CMOS signal to LVDS, and the receiver provides LVDS signal to CMOS. The data rate between of them can be up to 700Mhz. The LVDS transceiver is implemented in SMIC 0.18um Logic process.
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SMIC 0.18 LVDS Transceiver Receiver IP
- SMIC 0.18um LVDS Transceiver
- MIPI D-PHY v1.2/LVDS/TTL combo PHY&Controller(supporting CSI/DSI)
- V-by-One Receiver PHY IP (Silicon Proven in SMIC 40LL)
- LVDS Transmitter PHY IP, Silicon Proven in SMIC 14SF+
- MIPI C-PHY Combo PHY & Controller (support combo TTL, LVDS, HiSPI)
- V-by-One Transmitter PHY IP (Silicon Proven in SMIC 40LL)