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SMIC 0.15um Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Diffusion ROM Compiler
The compiler supports a comprehensive range of words and bits. While satisfying speed and power requirements, it was optimized for area efficiency.
VeriSilicon SMIC Synchronous Memory Compiler uses four layers within the blocks and supports metal 4, 5, 6 or 7 as the top metal. Dummy bit cells are designed in with the intention to enhance reliability.
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SMIC IP
- Low Jitter PLL with Accurately Spaced 16-Phase Output Clocks
- Ultra Low Area Frequency Synthesizer PLL (3nm - 90nm)
- 32kHz Ultra-Fast-Lock IoT PLL
- Complete USB Type-C Power Delivery PHY, RTL, and Software
- USB 2.0 nanoPHY in SMIC (65nm)
- Duet Package of Embedded Memories and Logic Libraries for SMIC (65nm, 40nm)