The SMIC 0.13um Low Leakage APLL is a programmable Analog PLL suitable for high speed clock generation. The high speed VCO of this PLL can run up to 1000MHz. It contains a 64 (max) input clock divider, a 128 (max) feedback clock divider and an 8 (max) output clock divider. By setting PLL_DM, PLL_DN and PLL_DP to different values, the output clock will be locked at different multiples of the input frequency.
A lock indicator is also included in this PLL. Its output shows whether the output clock is at the right multiples of the input clock.
- Process: SMIC 0.13um Low Leakage 1.5V/3.3V 1P6M CMOS logic process
- Supply voltage: 1.4V~1.5V~1.6V
- Current: ~8mA
- Operating junction temperature: - 40°C ~ +25°C ~ +125°C
- Two outputs:
- - PLL_CLKO: standard output from the output divider
- - PLL_CLK: output from VCO directly