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SMIC 0.13um General Process, 1.2V/2.5V Standard I/O Library
VeriSilicon SMIC 0.13um 1.2V/2.5V I/O Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corporation (SMIC) 0.13um 1.2V/2.5V process. This library can take 3.3V tolerance. This library supports both Stagger I/O pads and Inline I/O pads. They are configurable and variable driving strength between 2mA - 24mA.
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Standard I/O IP
- SMIC 0.13um General Process, 1.2V/3.3V Standard I/O Library
- HSTL I/O Interface - TSMC 12nm 12FFC,FFC+
- 1.8V Secondary Oxide DDRx & LPDDRx Combo I/O Interface - TSMC 40nm 40G,LP,LP_eF,ULP,ULP_eF
- DDR4/3 & LPDDR4/3/2 I/O - TSMC 40nm 40G,LP,LP_eF,ULP,ULP_eF
- DDRx & LPDDRx Combo I/O Interface - TSMC 28nm 28HP, 28HPx, 28LP, 28ULP
- DDRx & LPDDRx Combo I/O Interface - TSMC 40nm 40G 40LP 40ULP