16bit 5Gsps silicon proven High performance Current Steering DAC IP Core
You are here:
SMIC 0.13um 1.2v APLL
This IP is a programmable Analog PLL suitable for high speed clock generation. The high speed VCO of this PLL can run up to 1000MHz. It contains a 1-64 input clock divider, a 1-128 feedback clock divider and a 1-8 output clock divider. By setting PLL_DM, PLL_DN and PLL_DP to different values, the output clock will be locked at different multiples of the input frequency.
A lock indicator is also included in this PLL. Its output shows whether the output clock is at the right multiples of the input clock.
A lock indicator is also included in this PLL. Its output shows whether the output clock is at the right multiples of the input clock.
查看 SMIC 0.13um 1.2v APLL 详细介绍:
- 查看 SMIC 0.13um 1.2v APLL 完整数据手册
- 联系 SMIC 0.13um 1.2v APLL 供应商