USB 3.2 Gen2/Gen1 PHY IP in TSMC(5nm, 6nm, 7nm,12nm/16nm, 22nm, 28nm, 40nm, 55nm)
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SMIC 0.13um 1.2v/3.3v PLL
This PLL is designed for audio clock generation. The reference clock is 13.5MHz crystal or the input clock. It supports 256*fs clock output and 384*fs clock output, where fs is the audio system sample rate of 32kHz/44.1kHz/48kHz. It integrates a phase frequency detector (PFD), a loop filter (LP), a voltage control oscillator (VCO), a current reference, two programmable dividers and other supportive circuits.
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