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SMIC 0.13um 1.2v/3.3v PLL
This PLL is designed for audio clock generation. The reference clock is 13.5MHz crystal or the input clock. It supports 256*fs clock output and 384*fs clock output, where fs is the audio system sample rate of 32kHz/44.1kHz/48kHz. It integrates a phase frequency detector (PFD), a loop filter (LP), a voltage control oscillator (VCO), a current reference, two programmable dividers and other supportive circuits.
特色
- Process: SMIC 0.13um 1P6M 1.2v/3.3v Logic Process
- Supply voltage: 3.3v +/-10%; 1.2v+/-10%
- Reference input: 13.5MHz crystal or external clock
- Clock output: fs*256(384) fs=48KHz/44.1KHz / 32KHz / 24KHz / 22.05KHz / 16KHz / 12KHz / 11.025KHz / 8KHz
- Output duty cycle: 49~51%
- Current: <1.5mA
- Operating temperature: 0~85C
查看 SMIC 0.13um 1.2v/3.3v PLL 详细介绍：
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