Original Lossless codec IP core - Full HD 30fps@126MHz (1Sample/clk)
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SMBUS Master IP
SMBUS Master interface provides full support for the two-wire SMBUS Master synchronous serial interface, compatible with SMBUS version 3.1 specification. Through its SMBUS Master compatibility, it provides a simple interface to a wide range of low-cost devices. SMBUS Master IIP is proven in FPGA environment. The host interface of the SMBUS Master can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.
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smbus IP
- TSMC 6nm (6FF) 3.3V SMBUS (I2C) IO
- TSMC 7nm (7FF) 3.3V SMBUS (I2C) IO
- I2C & SMBus Controller
- High speed 3.3V I/0 Library with 8kV ESD protection in TPSCo 65nm technology
- IO & ESD solutions supporting GPIO, I2C,RGMII, SD, LVDS, HDMI & analog/RF across multiple technology nodes
- A 28nm Wirebond IO library with dynamically switchable 1.8V/ 3.3V GPIO, 5V I2C open-drain, 1.8V & 3.3V analog, OTP program cell, and HDMI & LVDS protection macros - featured across a variety of metal stack and pad configuration options