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SLVS-EC Interface for FPGA
SLVS-EC v3.0 Rx IP is an interface IP core that runs on Altera® FPGAs. Using this IP, you can quickly and easily implement products that support the latest SLVS-EC standard v3.0. You will also receive an "Evaluation kit" for early adoption.
* Altera® FPGAs can receive signals directly from the SLVS-EC Interface.
* Compatible with the latest SLVS-EC Specification Version 3.0.
* Supports powerful De-Skew function. Enables board design without considering Skew that occurs between lanes.
* "Evaluation kit”(see below) is available for speedy evaluation at the actual device level.
* Altera® FPGAs can receive signals directly from the SLVS-EC Interface.
* Compatible with the latest SLVS-EC Specification Version 3.0.
* Supports powerful De-Skew function. Enables board design without considering Skew that occurs between lanes.
* "Evaluation kit”(see below) is available for speedy evaluation at the actual device level.
查看 SLVS-EC Interface for FPGA 详细介绍：
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Block Diagram of the SLVS-EC Interface for FPGA
SLVS-EC interface IP
- Camera SLVS-EC 3.0 Receiver 10.0Gbps 8-Lane
- Camera SLVS-EC/MIPI D-PHY/sub-LVDS/CMOS1.8 combo Receiver 5.0G/2.5G/1Gbps/166MHz 8-Lane
- Camera SLVS-EC 2.0 Receiver 5.0Gbps 8-Lane
- Camera SLVS-EC 3.0 Transmitter 10.0Gbps 8-Lane
- Camera SLVS-EC v.2.0 5.0Gbps / MIPI D-PHY v2-1 4.5Gbps combo Receiver 4-Lane
- Camera SLVS-EC/MIPI D-PHY/sub-LVDS/CMOS1.8 combo Receiver 2.4G/2.5G/800Mbps/166MHz 8-Lane