Single Precision Floating Point Complex Multiplier
Single precision(32bits) IEEE 754- 2008 standard Floating Point pipeline complex multiplier IP core achieve the high throughput in the FPGA/ASIC platforms. In Stratix-III FPGA Device it can achieve maximum operating clock frequency of 160MHz and throughput of 160MSPS with 8 clock cycle initial latency.
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Single Precision Floating Point Complex Multiplier
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Single Precision Floating Point Complex Multiplier
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Single Precision Floating Point Complex Multiplier
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