MIPI C-PHY v1.2 D-PHY v2.1 TX 2 trios/2 Lanes in TSMC (16nm, 12nm, N5)
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Single Port SRAM compiler - Memory optimized for ultra high density and high speed - compiler range up to 64 k
Single Port SRAM compiler - TSMC 130 nm BCD Plus - Memory optimized for ultra high density and high speed - compiler range up to 64 k
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