You are here:
Single Port SRAM Compiler IP, UMC 0.13um LL process
UMC 0.13um LL Logic/FSG process high density synchronous high density Single Port SRAM memory compiler.
查看 Single Port SRAM Compiler IP, UMC 0.13um LL process 详细介绍：
- 查看 Single Port SRAM Compiler IP, UMC 0.13um LL process 完整数据手册
- 联系 Single Port SRAM Compiler IP, UMC 0.13um LL process 供应商
Memory IP
- The SST SuperFlash® IP is an embedded CMOS Flash memory IP with sector/chip Erase and byte Program capability.
- HBM Subsystem IP Gen2
- High Performance DDR4/3 Memory Controller
- High-Speed, High-Density and Low Power Memory Compilers and Logic Libraries for TSMC (65nm, 40nm, 28nm, 16nm)
- Hyperbus Flash Memory Controller
- sROMet compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 1M