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Single Port SRAM Compiler IP, UMC 0.11um SP process
UMC 0.11um eFlash SP process, Single Port SRAM compiler.
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Memory IP
- The SST SuperFlash® IP is an embedded CMOS Flash memory IP with sector/chip Erase and byte Program capability.
- HBM Subsystem IP Gen2
- High Performance DDR4/3 Memory Controller
- SD 3.0 / SDIO 3.0 Combo Device Controller
- High-Speed, High-Density and Low Power Memory Compilers and Logic Libraries for TSMC (65nm, 40nm, 28nm, 16nm)
- Hyperbus Flash Memory Controller