Highly powerful and scalable multi-mode communication processor for IoT wireless applications
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Single Port SRAM Compiler IP, 4.0um2 bit cells, High density, Low Power, UMC 0.18um G2 process
UMC 0.18um GII Logic process synchronous high density, Low Power mini Single Port SRAM.
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Memory IP
- The SST SuperFlash® IP is an embedded CMOS Flash memory IP with sector/chip Erase and byte Program capability.
- HBM Subsystem IP Gen2
- High Performance DDR4/3 Memory Controller
- High-Speed, High-Density and Low Power Memory Compilers and Logic Libraries for TSMC (65nm, 40nm, 28nm, 16nm)
- Hyperbus Flash Memory Controller
- sROMet compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 1M