MIPI D-PHY Rx-Only 2 Lanes in TSMC (40nm, 28nm, 22nm, 16nm, 12nm, N7, N6)
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Single-port 16/32/64-bit DDR266 Controller
The Single-port 16/32/64 bit DDR266 controller IP core is a DDR266 SDRAM controller AMBA AHB back-end. The controller can interface two 16-, 32- or 64-bit DDR266 memory banks to a 32-bit AHB bus. The controller acts as a slave on the AHB bus where it occupies a configurable amount of address space for DDR SDRAM access. The DDR controller is programmed by writing a configuration register mapped located in AHB I/O address space.
Internally, the core consists of an AHB/DDR controller and a technology specific DDR PHY.
Internally, the core consists of an AHB/DDR controller and a technology specific DDR PHY.
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Single-port 16/32/64-bit DDR266 Controller IP
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