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Single Lane and Quad Lane 8Gbps PCIe3.0 PHY IP in GF 28SLP process
TERMINUS-CIRCUITS PCIe GEN3.0 PHY is high performance, low power, low latency Single &Quad-Lane PCI Express PHY that supports PCI Express protocol and its signalling needs. It has features like clocking and clock & Data recovering, Serialization and De-Sterilization of Data, 128/130b, data coding, Receiver detection.
TERMINUS-CIRCUITS’s PCIe GEN 3.0 PHY uses 32/16bit Data PIPE interface. It also supports lower power management states like L0s, L1, L1-sub-states and L2. PCIe Gen 3.0 PHY IP is available in GF 28nm SLP process.
* A limited number of Test Chips manufactured in GF 28SLP (Single lane and Quad Lanes) are available for Early customers. Contact us for more details.
TERMINUS-CIRCUITS’s PCIe GEN 3.0 PHY uses 32/16bit Data PIPE interface. It also supports lower power management states like L0s, L1, L1-sub-states and L2. PCIe Gen 3.0 PHY IP is available in GF 28nm SLP process.
* A limited number of Test Chips manufactured in GF 28SLP (Single lane and Quad Lanes) are available for Early customers. Contact us for more details.
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PCIe 3.0 PHY IP
- PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC
- USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP, Silicon Proven in TSMC 22ULP
- 1 to 64 Gbps PCI-Express (PCIe) 6.0 and CXL 3.0 PHY
- PCIe 6.0 PHY in TSMC (N6, N5, N4P, N3P, N3E)
- PCIe 6.0 PHY in Samsung (SF5A, SF4X, SF2)
- PCIe 7.0 PHY IP supporting the latest features of the evolving PCIe 7.0 specification to enable 128 GT/s and up to x16 lane configurations