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Single Lane and Quad Lane 5Gbps PCIe2.0 PHY IP in TSMC 55LP process
TERMINUS CIRCUITS PCIe GEN2.0 PHY is high performance, low power, low latency Single & Quad-Lane PCI Express PHY that supports PCI Express protocol and its signalling needs. It has features like clocking and clock & Data recovering, Serialization and De-Serialization of Data, 8/10b, data coding, Receiver detection.
TERMINUS CIRCUITS PCIe GEN 2.0 PHY uses 32/16bit Data PIPE interface. It also supports lower power management states like L0s, L1, L1-sub-states and L2. PCIe Gen 2.0 PHY IP is available in TSMC 55nm LP process.
* A limited number of Test Chips manufactured in TSMC 55LP (Single lane and Quad Lanes) are available for Early customers. Contact us for more details.
TERMINUS CIRCUITS PCIe GEN 2.0 PHY uses 32/16bit Data PIPE interface. It also supports lower power management states like L0s, L1, L1-sub-states and L2. PCIe Gen 2.0 PHY IP is available in TSMC 55nm LP process.
* A limited number of Test Chips manufactured in TSMC 55LP (Single lane and Quad Lanes) are available for Early customers. Contact us for more details.
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PCIe 5.0 PHY IP
- PCIe 5.0 PHY in TSMC (16nm)
- PHY/PCS Logical Sub-Block IP Core for PCIe supporting PCIe 5.0, 4.0, 3.1 PHY/PMA and compliant to the PIPE 5.2 and 4.4.1 Specifications
- PCIe 5.0 SerDes PHY
- PCIe 5.0 Customizable Embedded Multi-port Switch
- PCIe 5.0 Controller supporting Endpoint, Root Port, Switch, Bridge and advanced features
- PCIe 5.0 Controller with AMBA AXI interface