55nmHV MTP Non Volatile Memory for Standard CMOS Logic Process
Single Lane and Quad Lane 5Gbps PCIe2.0 PHY IP in GF 28SLP process
TERMINUS CIRCUITS PCIe GEN 2.0 PHY uses 32/16bit Data PIPE interface. It also supports lower power management states like L0s, L1, L1-sub-states and L2. PCIe Gen 2.0 PHY IP is available in GF 28SLP process.
* A limited number of Test Chips manufactured in GF28SLP (Single lane and Quad Lanes) are available for Early customers. Contact us for more details.
查看 Single Lane and Quad Lane 5Gbps PCIe2.0 PHY IP in GF 28SLP process 详细介绍:
- 查看 Single Lane and Quad Lane 5Gbps PCIe2.0 PHY IP in GF 28SLP process 完整数据手册
- 联系 Single Lane and Quad Lane 5Gbps PCIe2.0 PHY IP in GF 28SLP process 供应商
PCIe 5.0 PHY IP
- PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC
- PCIe 5.0 PHY in TSMC (16nm, 12nm, N7, N6, N5, N4P, N3E, N3P)
- PCIe 5.0 Controller supporting Endpoint, Root Port, Switch, Bridge and advanced features
- PCIe 5.0 Controller with AMBA AXI interface
- PCIe 5.0 Customizable Embedded Multi-port Switch
- PCIe 5.0 PHY IP for Storage and High-Bandwidth Connection