Single Lane and Quad Lane 16Gbps PCIe4.0 PHY IP in TSMC 28HPC process
TERMINUS CIRCUITS PCIe GEN 4.0 PHY uses 32/16bit Data PIPE interface. It also supports lower power management states like L0s, L1, L1-sub-states and L2. PCIe Gen 4.0 PHY IP is available in TSMC 28nm HPC/HPC+ process.
* A limited number of Test Chips manufactured in TSMC 28HPC (Single lane and Quad Lanes) are available for Early customers. Contact us for more details.
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PCIe 4.0 PHY IP
- PCIe 4.0 PHY IP with 16GT/s optimized for low power consumption (Silicon Proven in TSMC 28HPC+)
- PHY/PCS Logical Sub-Block IP Core for PCIe supporting PCIe 5.0, 4.0, 3.1 PHY/PMA and compliant to the PIPE 5.2 and 4.4.1 Specifications
- 32G Multi-protocol SerDes PHY
- PCIe 4.0 PHY in GlobalFoundries (14nm)
- PCIe 4.0 PHY in Samsung (14nm)
- PCIe 4.0 PHY in TSMC (28nm, 16nm, 12nm, 7nm)