The Western Digital SweRV Core™ EL2 is a single issue, RV32IMC, single-issue core with a 4-stage in-order pipeline. Like the EH1 and EH2, it supports optional instruction and data closely coupled memories with ECC protection and optional 2- or 4-way set-associative instruction cache with parity or ECC protection (32- or 64-byte line size). It is rated at 3.6 CoreMark/MHz. The core has been open sourced through CHIPS Alliance.
The SweRV Core Support Package (SCSP) contains everything needed to deploy a Western Digital SweRV™ EL2 core in an integrated circuit providing support for both EDA tool flows and embedded software development. SCSP saves the considerable effort that would be needed to set up EDA flows for the EL2 core from scratch.
The SweRV Core Support Package for EL2 is available in both basic Free and Pro versions.
The Free version consists of open-source deliverables and infrastructure for using open-source EDA tools and an SDK. Users can access a forum for support.
The Pro version combines open source and commercial deliverables. It provides flows, examples and models for using commercial EDA tools. This version includes professional support.
- SwerRV Core EL2
- RV32IMC instructions
- Single issue
- 4-stage pipeline
- 2 stall points
- Instruction cache
- 3.6 CoreMarks/MHz
- 0.023mm2 in TSMC 16 nm
- SweRV Core Support Package for EL2 Core
- Free and Pro versions
- Support for open and commercial EDA tools
- Emulation using Digilent FPGA board
- Examples of bare metal and FreeRTOS
- The SweRV Core Support Package provides a low risk way of deploying the SweRV Core EL2 core with either open-source or commercial EDA tools.
- Pre-defined EDA flows with differences between specific EDA tools abstracted from the user.
- The package is complete supporting embedded software development, emulation, implementation and comprehensive debug.
- The offering is flexible depending on the complexity of the EDA flows required.
- SweRV Core Support Package Free Version
- Western Digital EL2 open RTL
- IP-specific flows for open EDA tools
- Western Digital Whisper ISS
- RISC-V GNU toolchain
- Eclipse IDE
- Open OCD debugging tool
- Codasip infrastructure for EDA & IP
- User forum
- SweRV Core Support Package Pro Version contains additionally
- Flows for commercial simulators
- Flows for commercial synthesis tools
- Flows for commercial static code analysis
- Tools and equivalence checking
- Professional support from Codasip
- Medium-performance 32-bit embedded applications such as storage, motor control, database engines and control systems for appliances.
Block Diagram of the Single issue, embedded RISC-V core with 4-stage pipeline