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Single, Dual and Quad SPI Flash Controller with Boot and Execute On-The-Fly Features
The core automatically identifies a variety of serial flash memories and communicates with the attached device at the maximum possible bandwidth. Register accesses are used to insert access requests and read/write data into/out SPI-MEM-CTRL core. Communication with devices other than those automatically identified, is also feasible as the core can be programmed with the memory device parameters. The SPI-MEM-CTRL can read, write or erase any part of the memory.
The core is rigorously verified. A complete verification environment that helps designers verify the functionality and compliance of the core, and additional aids for system-level simulation are available.
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Block Diagram of the Single, Dual and Quad SPI Flash Controller with Boot and Execute On-The-Fly Features

SPI Flash Controller IP
- Flash SPI controller master/slave
- SPI Flash Memory Controller
- SPI FLASH Controller with Execute in place – XIP (SINGLE, DUAL and QUAD SPI Bus Controller with DDR / DTR support and optional AES Encryption)
- Quad-SPI FLASH Controller AHB
- xSPI NOR Flash controller
- AXI / AHB / APB - SPI Flash Memory Controller - Octal/Quad/Dual/Single SPI I/O - CPU access to Flash and optional Execute-in-Place (XIP), Boot, DMA