The HDLC Controller cores consist of a Receiver (FPR: From Primary Rate) and a Transmitter (TPR: To Primary Rate) unit. These single channel HDLC controllers handle all interframe flags, delimiting flags and Frame Check Sequence (FCS) pattern. The FCS is calculated using a CRC-16 polynomial.
The HDLC protocol has several subsets (e.g., Q.921, Q922, X.25 etc.). The structure of a frame (header, trailer, FCS, stuffing/destuffing) is the same but the procedures for Commands, Responses and Abort Conditions are different and are handled by software. iniHDLC cores can be used within the whole HDLC subset.
The The HDLC Controller cores are a synthesiszable, flexible, and structured VHDL implementation of the HDLC protocol. The cores are designed for easy interfacing to custom buffers (e.g., FIFO, DMA-Interface).
- Single Port Interface
- Transparent Mode
- Start- and Stopflag Generation/Detection
- Frame Check Sequence Generation/Verification (CRC-16)
- Built-in Bit Stuffing/Destuffing
- Frame Status Signalling
- Clock to Baud Ratio up to 1:1
- Supporting Protocols: Q.921(LAPD) ISDN, Q.922 Frame Relay, X.25 (LAPB) PBX , WAN...and more
- Flexible I/O Interface towards FIFO, uP, RAM and DMA
- Full synchronous operation
- Easy interfacing to customers requirements such as
- Interrupt controled data transfer
- Direct memory access using built-in DMA controller
- On-chip dual-port memory for temporary buffering of frame
- VHDL or Verilog RTL Source Code
- Functional Testbench
- Synthesys Script
- Data Sheet
- User Guide
- Hotline Support by means of phone, fax and e-mail
Block Diagram of the Single Channel HDLC Controller