You are here:
HDLC Controller
The HDLC Controller cores consist of a Receiver (FPR: From Primary Rate) and a Transmitter (TPR: To Primary Rate) unit. These single channel HDLC controllers handle all interframe flags, delimiting flags and Frame Check Sequence (FCS) pattern. The FCS is calculated using a CRC-16 polynomial.
The HDLC protocol has several subsets (e.g., Q.921, Q922, X.25 etc.). The structure of a frame (header, trailer, FCS, stuffing/destuffing) is the same but the procedures for Commands, Responses and Abort Conditions are different and are handled by software. iniHDLC cores can be used within the whole HDLC subset.
The The HDLC Controller cores are a synthesiszable, flexible, and structured VHDL implementation of the HDLC protocol. The cores are designed for easy interfacing to custom buffers (e.g., FIFO, DMA-Interface).
The HDLC protocol has several subsets (e.g., Q.921, Q922, X.25 etc.). The structure of a frame (header, trailer, FCS, stuffing/destuffing) is the same but the procedures for Commands, Responses and Abort Conditions are different and are handled by software. iniHDLC cores can be used within the whole HDLC subset.
The The HDLC Controller cores are a synthesiszable, flexible, and structured VHDL implementation of the HDLC protocol. The cores are designed for easy interfacing to custom buffers (e.g., FIFO, DMA-Interface).
查看 Single Channel HDLC Controller 详细介绍：
- 查看 Single Channel HDLC Controller 完整数据手册
- 联系 Single Channel HDLC Controller 供应商
Block Diagram of the Single Channel HDLC Controller
