This PLL is designed for audio clock generation. The reference clock is 12MHz, 13.5MHz or 19.2MHz, which can be either from the crystal OSC or from internal clock source. It supports 256*fs and 128*fs clock outputs, where fs is the audio system sample rate of 8k/11k/12k/16k/22k/24k/32kHz/44.1kHz/48kHz/192k. The IP integrates a phase frequency detector (PFD), a loop filter (LP), a voltage control oscillator (VCO), a current reference, two programmable dividers and other supportive circuits.
- Process: SMIC 65nm LL 1.2v/1.8v/2.5v 1P8M CMOS Logic process Supply voltage: 1.2v +/-10%; 2.5v +/-10%
- Reference input: 12MHz, 13.5MHz or 19.2MHz
- Clock output: 24.572MHz, 12.286MHz, 11.294MHz, 8.190MHz, 6.143MHz, 5.647MHz, 4.095MHz, 3.071MHz, 2.823MHz, 2.048MHz
- Output duty cycle: 45~55%
- Current: <3.5mA
- Operating temperature: -40~125°C