USB 3.2 Gen2/Gen1 PHY IP in TSMC(5nm, 6nm, 7nm,12nm/16nm, 22nm, 28nm, 40nm, 55nm)
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SilTerra 0.18um 1.8V APLL
This IP is a programmable Analog PLL suitable for high speed clock generation. The high speed VCO can run from 200MHz to 600MHz. It contains a 1-64 input clock divider (DM), a 1-128 feedback clock divider (DN), a 1-8 output clock divider (DP).
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