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Serial RapidIO - Physical Layer Interface
	The Serial RapidIO core supports the physical layer specification as defined in the RapidIO Specification Rev 1.2. The Serial RapidIO Physical Layer defines a protocol for packet delivery between Serial RapidIO devices and other devices, including packet transmission, flow control, error management and link maintenance protocols. The core supports one-lane high speed (1x mode) running at 1.0, 2.0 Gbps or a maximum of 2.5 Gbps. This Serial RapidIO core is optimized to support ORT82G5/ORT42G5 FPSCs.
 
		
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Block Diagram of the Serial RapidIO - Physical Layer Interface
	FPGA IP
- RT-630-FPGA Hardware Root of Trust Security Processor for Cloud/AI/ML SoC FIPS-140
 - Complete USB Type-C Power Delivery PHY, RTL, and Software
 - Ethernet TSN Switch IP Core - Efficient and Massively Customizable
 - CXL 2.0 Agilex FPGA Acclerator Card
 - PCIe Gen3 to SRIO Gen3 Bridge (FPGA)
 - 65nm/40nm Low Power eFPGA IP and Open Source FPGA Software
 



