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Serial-ATA (SATA) I/II Host Controller
The so_ip_sata2_hctrl is a soft core implementation of SATA host controller as defined in the SATA specification 2.6.
So_ip_sata2_hctrl soft core is fully compliant with the SATA 2.6 specification, and supports both 1.5 Gbit/s and 3.0 Gbit/s data transfer rates.
So_ip_sata2_hctrl core implements physical, link and transport layers defined in the SATA 2.6 specification. It can use both RocketIO GTP and GTX transceivers to implement required physical signaling. For the interface with the host processor IP core uses standard PATA interface, and for the interface with the DMA engine simple TX and RX transaction interface.
So_ip_sata2_hctrl core is delivered with fully automated testbench and a compete set of tests allowing easy package validation at each stage of SoC design flow.
The so_ip_sata2_hctrl design is strictly synchronous with positive-edge clocking, no internal tri-states and a synchronous reset. It operates at 37.5 MHz system clock frequency in case of SATA-I mode (1.5 Gbit/s data transfer rate) and at 75 MHz in case of SATA-II mode (3.0 Gbit/s data transfer rate).
The so_ip_sata2_hctrl core can be evaluated using Xilinx Evaluation Platforms before actual purchase. This is achieved by using a time-limited demonstration bit files for ML-505/506/507 platforms that allows the user to connect it’s HDD to the SATA core and evaluate system performance under different transfer scenarios.
So_ip_sata2_hctrl soft core is fully compliant with the SATA 2.6 specification, and supports both 1.5 Gbit/s and 3.0 Gbit/s data transfer rates.
So_ip_sata2_hctrl core implements physical, link and transport layers defined in the SATA 2.6 specification. It can use both RocketIO GTP and GTX transceivers to implement required physical signaling. For the interface with the host processor IP core uses standard PATA interface, and for the interface with the DMA engine simple TX and RX transaction interface.
So_ip_sata2_hctrl core is delivered with fully automated testbench and a compete set of tests allowing easy package validation at each stage of SoC design flow.
The so_ip_sata2_hctrl design is strictly synchronous with positive-edge clocking, no internal tri-states and a synchronous reset. It operates at 37.5 MHz system clock frequency in case of SATA-I mode (1.5 Gbit/s data transfer rate) and at 75 MHz in case of SATA-II mode (3.0 Gbit/s data transfer rate).
The so_ip_sata2_hctrl core can be evaluated using Xilinx Evaluation Platforms before actual purchase. This is achieved by using a time-limited demonstration bit files for ML-505/506/507 platforms that allows the user to connect it’s HDD to the SATA core and evaluate system performance under different transfer scenarios.
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