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Secure Hash Algorithm-3 (256 bit digest) IP Core
XIP3032H from Xiphera is a high-speed Intellectual Property (IP) core implementing the Secure Hash Algorithm-3 with a 256 bits long message digest (hash). The SHA-3 family of hash functions are based on the Keccak sponge function, and their internal structure is different from the SHA-2 family of hash functions which are based on the Merkle-Damgård structure. The hashing speeds achieved with FPGA-based implementations of SHA-3 are faster than those achieved with SHA-2, and consequently SHA-3 hash functions are a strong candidate for applications where the primary goal is to maximimize throughput.
XIP3032H has been designed for easy integration with FPGA- and ASIC-based designs in a vendor-agnostic design methodology, and the functionality of XIP3032H does not rely on any FPGA manufacturer-specific features.
XIP3032H has been designed for easy integration with FPGA- and ASIC-based designs in a vendor-agnostic design methodology, and the functionality of XIP3032H does not rely on any FPGA manufacturer-specific features.
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Block Diagram of the Secure Hash Algorithm-3 (256 bit digest) IP Core
