Perceptia’s DeepSub™ pPLL02F is a low-power clocking PLL. This PLL is part of Perceptia's second generation digital PLLs, providing low-power fractional-N (and integer-N) operation. It delivers output clock frequencies up to 2GHz (in GF22FDX).
Because the PLL is all-digital, it is also the smallest PLL IP in the industry. It features Perceptia proprietary and patented technology that enables it to be faster and more stable than a comparable analog PLL, at a fraction of the die size. The design includes dedicated DSP circuits to minimize influences of the process, voltage, and temperature (PVT) on the loop behavior.
pPLL02F can be used as an integer-N PLL or as a fractional-N PLL. The fractional-N mode provides a high flexibility to choose the best combination of input and output clock frequencies at the system level.
The IP uses two supply voltages, one for its digital core and one for mixed-signal circuits. The digital core supply may be shared with any other digital logic supply or alternatively the two supply pins may be connected to a single supply voltage. Jitter performance is improved by maintaining a separate, clean analog supply.
- Second-generation digital PLL architecture, providing integer and fractional multiplication
- Low power, suitable for logic clocking applications
- Extremely small die area, using a ring oscillator
- Twelve bits fractional resolution
- Reference clock from 5MHz to 500MHz (CK_XTAL_IN)
- A prescaler generates the internal reference frequency CK_REF as a division of the external reference (divide by 1 to 15)
- Internal reference from 5MHz to 125MHz (CK_REF)
- Output frequency can be from 1 to 400 times CK_REF, up to the maximum DCO frequency
- Two PLL outputs via separate postscalers
- Postscalers programmable from L = 1 to 2,040
- Configurable loop filter can be programmed to optimize performance for specific crystals or reference clock sources. Supports sub-kHz to MHz loop bandwidths. Default settings are optimized for a 25MHz or higher crystal.
- Lock-detect output
- Can generate a spread-spectrum clock (SSC) from a clean reference
- Can lock to an input clock with spread spectrum
- PLL output duty cycle better than 48 / 52% on CK_PLL_OUT0 and CK_PLL_OUT1
- Highly testable using industry standard flows
- ATPG vectors provided
- Specification of functional tests to supplement ATPG testing
- One digital and one mixed-signal power supply; both pins may be connected to a single supply in less jitter-sensitive applications
- General-purpose PLL
- Logic clocking
- SoC clock tree
- Mass-volume applications
Block Diagram of the Second-Generation Digital Fractional-N PLL for Logic Clocking