Increasing SoC/ASIC devices' complexity also demands increase in memory bandwidth. Single data rate devices are being replaced by double (and more) data rate devices in applications where memory bandwidth is essential. The development trend in DDR SDRAM devices is biased towards higher clock frequencies and higher latencies. Beyond DDR SDRAM Memory Controller IP Core was developed with this trend in mind. It interleaves accesses when possible, maximizing utilization of memory control and data buses. This reduces overall memory access latencies while utilizing its higher bandwidth capabilities.
Beyond DDR SDRAM Memory Controller IP Core provides access to external synchronous dynamic memory devices for SoC designs using WISHBONE SoC interconnect bus as internal bus. A wide variety of different memory device organizations and speeds are supported. Beyond DDR SDRAM Memory Controller IP Core also uses a lot of optional, compile time parameters, which makes it configurable for use in a wide variety of applications.