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SD 4.1 UHS-II PHY for TSMC 12nm FF
The rapid proliferation of high-performance mobile and handheld devices has resulted in increasing requirements for non-volatile memory. Memory interfaces with larger capacities and faster access times are needed.
In response to these trends, SD 4.1 UHS-II or sd 4.1 uhs-ii achieves a peak interface speed of 3.12Gb/s. Arasan’s UHS-II PHY is compliant with the draft specification of UHS-II and is an extremely area and power efficient implementation. This interface is backward compatible with legacy SD cards. Both Host and Device UHS-II PHY configurations are available
The UHS-II PHY IP is a comprehensive, silicon-proven configurable core that has been ported to multiple process nodes and leading foundries. It uses sub-LVDS signaling consisting of one pair each for transmit, receive and an additional reference clock. This low-pin interface has reduced power consumption and low EMI. To further reduce power, the reference clock operates at 1/15 or 1/30 of the data transfer speed. This differential clock operates between 26MHz to 52MHz and is carried over the legacy SD lines DAT0, DAT1.
Arasan’s SD 4.1 UHS II PHY operates in both the Full-duplex and Half-duplex modes. It includes a 8b/10b encoder/decoder. The controller side interface of the UHS II PHY operates in the range from 39MB/s to 156MB/s. The default data lane D0 is used for downstream connection and the D1 lane is used for the other direction. An 8b/10b coding scheme is used. To improve testability, the SD 4.1 UHS II PHY implements the standard loopback paths.
In response to these trends, SD 4.1 UHS-II or sd 4.1 uhs-ii achieves a peak interface speed of 3.12Gb/s. Arasan’s UHS-II PHY is compliant with the draft specification of UHS-II and is an extremely area and power efficient implementation. This interface is backward compatible with legacy SD cards. Both Host and Device UHS-II PHY configurations are available
The UHS-II PHY IP is a comprehensive, silicon-proven configurable core that has been ported to multiple process nodes and leading foundries. It uses sub-LVDS signaling consisting of one pair each for transmit, receive and an additional reference clock. This low-pin interface has reduced power consumption and low EMI. To further reduce power, the reference clock operates at 1/15 or 1/30 of the data transfer speed. This differential clock operates between 26MHz to 52MHz and is carried over the legacy SD lines DAT0, DAT1.
Arasan’s SD 4.1 UHS II PHY operates in both the Full-duplex and Half-duplex modes. It includes a 8b/10b encoder/decoder. The controller side interface of the UHS II PHY operates in the range from 39MB/s to 156MB/s. The default data lane D0 is used for downstream connection and the D1 lane is used for the other direction. An 8b/10b coding scheme is used. To improve testability, the SD 4.1 UHS II PHY implements the standard loopback paths.
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