180nm FTP Non Volatile Memory for Standard CMOS Logic Process
SD 3.0 / SDIO 3.0 / eMMC 5.0 Host Controller
The eMMC 5.0 / SD3.0 Host Controller IP supports connection to a single slot and performs multi-block writes and erases that lower access overhead. In addition, a host can utilize this IP to boot directly from an attached eMMC memory, thereby simplifying system initialization during power up. The host interface is based on a standard 32-bit AHB bus which is used to transfer data and configure the IP.
查看 SD 3.0 / SDIO 3.0 / eMMC 5.0 Host Controller 详细介绍:
- 查看 SD 3.0 / SDIO 3.0 / eMMC 5.0 Host Controller 完整数据手册
- 联系 SD 3.0 / SDIO 3.0 / eMMC 5.0 Host Controller 供应商
Block Diagram of the SD 3.0 / SDIO 3.0 / eMMC 5.0 Host Controller
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Video Demo of the SD 3.0 / SDIO 3.0 / eMMC 5.0 Host Controller
Arasan eMMC 5.0 Host Controller Hardware Validation Platform Demonstration