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Scatter-Gather DMA - AXI4-Stream to/from AXI4 Memory Map Transfers
The Digital Blocks DB-DMAC-MC-AXI4-MM-STREAM Verilog RTL IP Core is a Multi-Channel Scatter-Gather DMA Controller that transfers data between AXI4 Memory Map and AXI4-Stream Interfaces.
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Block Diagram of the Scatter-Gather DMA - AXI4-Stream to/from AXI4 Memory Map Transfers
AXI4-Stream Interface IP
- Very compact (500 LUTs) Camera Sensor Receiver Interface Converting from MIPI CSI-2 to AXI4-Stream Video Standard
- DMA AXI4-Stream Interface to AXI Memory Map Address Space
- Compute Express Link (CXL) 2.0 Controller with AMBA AXI interface
- CCIX 1.1 Controller with AMBA AXI interface
- Receives video data from Flir's Lepton IR-sensors, Video over SPI (VoSPI)
- PCIe Controller for USB4 Hosts and Devices supporting PCIe Tunneling, with optional built-in DMA and configurable AMBA AXI interface