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Scalable and Programmable Co-processor
This IP Core is a scalable and programmable co-processor for the signal processing of complex embedded digital signal processing (DSP) systems. This DSP IP Core is a scalable processor architecture that perfectly allies hardware computational power with the flexibility of software.
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Block Diagram of the Scalable and Programmable Co-processor
Coprocessor IP
- Secure-IC's Securyzr Crypto Coprocessor with integrated Post-Quantum Cryptography IPs
- Secure-IC's Securyzr(TM) Crypto Coprocessor (Standard)
- Secure-IC's Securyzr(TM) Crypto Coprocessor (Compact)
- Secure-IC's Securyzr(TM) Crypto Coprocessor (Premium)
- DES and Triple DES (TDES or 3DES) encryption and decryption coprocessor
- 16 bit DSP fixed point coprocessor