You are here:
Scalable and Programmable Co-processor
This IP Core is a scalable and programmable co-processor for the signal processing of complex embedded digital signal processing (DSP) systems. This DSP IP Core is a scalable processor architecture that perfectly allies hardware computational power with the flexibility of software.
查看 Scalable and Programmable Co-processor 详细介绍：
- 查看 Scalable and Programmable Co-processor 完整数据手册
- 联系 Scalable and Programmable Co-processor 供应商
Block Diagram of the Scalable and Programmable Co-processor
Coprocessor IP
- Secure-IC's Securyzr Crypto Coprocessor with integrated Post-Quantum Cryptography IPs
- Secure-IC's Securyzr(TM) Crypto Coprocessor
- DES and Triple DES (TDES or 3DES) encryption and decryption coprocessor
- Hardware accelerator for RSA, DSA, Diffie-Hellman, El-Gamal and Elliptic Curves algorithms
- Hardened 128-bit Advanced Encryption Standard (AES) coprocessor
- SHA-256 encryption and decryption coprocessor