Process Detector (For DVFS and monitoring process variation)
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SC12 Standard Cell Library - Samsung 65 nm CMOS10LP
ARM® Logic IP solutions are the ideal choice for advanced, deep submicron SoC designs. The Standard Cell Libraries are complemented by Power Management Kit and ECO Kit extensions, delivering optimal performance, power and area results.
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Logic IP IP
- Aeonic Generate Digital PLL for multi-instance, core logic clocking
- Duet Package of Embedded Memories and Logic Libraries for GF (55nm, 40nm, 22nm)
- Duet Package of Embedded Memories and Logic Libraries for Huali (55nm, 40nm)
- Duet Package of Embedded Memories and Logic Libraries for SMIC (65nm, 40nm)
- Duet Package of Embedded Memories and Logic Libraries for TSMC (65nm, 40nm, 28nm, 16nm, N7, N6, N5, N4P)
- Duet Package of Embedded Memories and Logic Libraries for UMC (40nm, 28nm)