MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, N7, N5A)
SC12 Arithmetic Tool Kit - GLOBALFOUNDRIES 65 nm CMOS10SF
查看 SC12 Arithmetic Tool Kit - GLOBALFOUNDRIES 65 nm CMOS10SF 详细介绍:
- 查看 SC12 Arithmetic Tool Kit - GLOBALFOUNDRIES 65 nm CMOS10SF 完整数据手册
- 联系 SC12 Arithmetic Tool Kit - GLOBALFOUNDRIES 65 nm CMOS10SF 供应商
Logic IP IP
- Aeonic Generate Digital PLL for multi-instance, core logic clocking
- H.264 Baseline Encoder with compressed reference frame store
- Duet Package of Embedded Memories and Logic Libraries for GF (55nm, 40nm, 22nm)
- Duet Package of Embedded Memories and Logic Libraries for Huali (55nm, 40nm)
- Duet Package of Embedded Memories and Logic Libraries for SMIC (65nm, 40nm)
- Duet Package of Embedded Memories and Logic Libraries for TSMC (65nm, 40nm, 28nm, 16nm, N7, N6, N5, N4P)