You are here:
SC10 Standard Cell Library - TSMC 55 nm CLN55GP
ARM® Logic IP solutions are the ideal choice for advanced, deep submicron SoC designs. The Standard Cell Libraries are complemented by Power Management Kit and ECO Kit extensions, delivering optimal performance, power and area results.
查看 SC10 Standard Cell Library - TSMC 55 nm CLN55GP 详细介绍：
- 查看 SC10 Standard Cell Library - TSMC 55 nm CLN55GP 完整数据手册
- 联系 SC10 Standard Cell Library - TSMC 55 nm CLN55GP 供应商
Logic IP IP
- Aeonic Generate Digital PLL for multi-instance, core logic clocking
- Duet Package of Embedded Memories and Logic Libraries for GF (55nm, 40nm, 22nm)
- Duet Package of Embedded Memories and Logic Libraries for Huali (55nm, 40nm)
- Duet Package of Embedded Memories and Logic Libraries for SMIC (65nm, 40nm)
- Duet Package of Embedded Memories and Logic Libraries for TSMC (65nm, 40nm, 28nm, 16nm, N7, N6, N5, N4P)
- Duet Package of Embedded Memories and Logic Libraries for UMC (40nm, 28nm)