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SATA 6G PHY in TSMC (40nm, 28nm, 16nm)
The DesignWare Mixed-Signal PHY IP for SATA and eSATA is designed for use in SoC solutions. The PHY integrates seamlessly with the DesignWare SATA AHCI Host digital controller to reduce design time and achieve first-pass silicon success. The SATA PHY provides a cost effective solution that is designed to meet the needs of today’s SATA designs. While extremely low in power consumption and area, the DesignWare SATA PHY substantially exceeds the electrical specifications in such key performance areas as jitter and receive sensitivity. The unique, advanced built-in diagnostics and sample automatic test equipment (ATE) test vectors available in the DesignWare PHY enable designers to implement complete at-speed production testing without expensive test equipment. Furthermore, the test vectors provide on-chip visibility into the actual link performance to quickly identify signal integrity issues.
The PHY includes a wide range of test capabilities including built-in per-channel BERTs, flexible fixed and random pattern generation, error counting on patterns or disparity, digital phase or voltage margining (bathtub curves), and built-in per channel scopes. The high-margin, robust SATA PHY architecture tolerates for manufacturing variations such as process, voltage and temperature. The SATA PHY passed interoperability testing utilizing industry-leading 65-nm, 40-nm, and 28-nm process technologies.
The PHY includes a wide range of test capabilities including built-in per-channel BERTs, flexible fixed and random pattern generation, error counting on patterns or disparity, digital phase or voltage margining (bathtub curves), and built-in per channel scopes. The high-margin, robust SATA PHY architecture tolerates for manufacturing variations such as process, voltage and temperature. The SATA PHY passed interoperability testing utilizing industry-leading 65-nm, 40-nm, and 28-nm process technologies.
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