You are here:
SATA 3 HOST IP on ARRIA 10 FPGA
The LDS-SATA3-HOST-A10GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Match FIFO on a INTEL ARRIA 10 GX FPGA. The LDS-SATA3-HOST-A10GX IP is compliant with Serial ATA III specification and signaling rate is 6Gbps. The LDS-SATA3-HOST-A10GX IP is fully synchronous with system frequency (Clock_sys) at 150MHz in case of 6Gbps speed and 75MHz in case of 3Gbs speed configuration. The VHDL source code format is available for ease of customization. The customization can be done by Logic Design Solutions and DO254 documentation is available on request.
查看 SATA 3 HOST IP on ARRIA 10 FPGA 详细介绍：
- 查看 SATA 3 HOST IP on ARRIA 10 FPGA 完整数据手册
- 联系 SATA 3 HOST IP on ARRIA 10 FPGA 供应商
Block Diagram of the SATA 3 HOST IP on ARRIA 10 FPGA
