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SATA 3 Host Controller on ARRIA V FPGA
The SATA 3 Host Controller IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Macth FIFO on a ALTERA Stratix IV GX FPGA.
The SATA 3 Host Controller IP is compliant with Serial ATA III specification and signaling rate is 6Gbps and scalable 3Gbs.
The SATA 3 Host Controller IP is fully synchronous with system frequency (Clock_sys) at 150MHz in case of 6Gbps speed selection and 75MHz in case of 3Gbs speed configuration. The VHDL source code format is available for ease of customization. The customization can be done by Logic Design Solutions and DO254 documentation is available on request.
The SATA 3 Host Controller IP is compliant with Serial ATA III specification and signaling rate is 6Gbps and scalable 3Gbs.
The SATA 3 Host Controller IP is fully synchronous with system frequency (Clock_sys) at 150MHz in case of 6Gbps speed selection and 75MHz in case of 3Gbs speed configuration. The VHDL source code format is available for ease of customization. The customization can be done by Logic Design Solutions and DO254 documentation is available on request.
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Block Diagram of the SATA 3 Host Controller on ARRIA V FPGA
