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RXAUI
Xilinx provides a no charge Dune Network compliant RXAUI core to ensure first time success in your design.
No charge parameterizable core that utilizes the Kintex® UltraScale™, Virtex® UltraScale Virtex-7, Artix®-7, Kintex-7, Viratex-7, Zynq®-7000, and Virtex-6 Transceivers to support the RXAUI function.
The Xilinx Reduced 10 Gigabit Attachment Unit Interface (RXAUI) LogiCORE™ IP provides a 2-lane high speed serial interface at 6.25 Gbps, providing up to 10 Gigabits per second (Gbps) total throughput for Dune Networks RXAUI specification. Operating at an internal clock speed of 156.25 MHz, the core includes the XGMII Extender Sublayers (DTE and PHY XGXS), and the 10GBASE-X sublayer, as described in clauses 47 and 48 of IEEE 802.3-2012. In addition, the core supports an optional serial MDIO management interface for accessing the IEEE 802.3-2012 clause 45 management registers. The MDIO interface may be omitted to save logic, in which case a simplified management interface is provided via bit vectors.
No charge parameterizable core that utilizes the Kintex® UltraScale™, Virtex® UltraScale Virtex-7, Artix®-7, Kintex-7, Viratex-7, Zynq®-7000, and Virtex-6 Transceivers to support the RXAUI function.
The Xilinx Reduced 10 Gigabit Attachment Unit Interface (RXAUI) LogiCORE™ IP provides a 2-lane high speed serial interface at 6.25 Gbps, providing up to 10 Gigabits per second (Gbps) total throughput for Dune Networks RXAUI specification. Operating at an internal clock speed of 156.25 MHz, the core includes the XGMII Extender Sublayers (DTE and PHY XGXS), and the 10GBASE-X sublayer, as described in clauses 47 and 48 of IEEE 802.3-2012. In addition, the core supports an optional serial MDIO management interface for accessing the IEEE 802.3-2012 clause 45 management registers. The MDIO interface may be omitted to save logic, in which case a simplified management interface is provided via bit vectors.
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Interface and Interconnect IP
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- Universal Chiplet Interconnect Express (UCIe) Controller
- Serial Peripheral Interconnect Master & Slave Interface Controller
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- Physical Layer Interface Core
- PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC