MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, 12nm, N7, N6, N5, N3E)
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ROM Compiler IP, UMC 0.162um G2 process
UMC 0.162um GII Logic process synchronous Via-1 programmable ROM memory compiler.
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