MIPI C-PHY v1.2 D-PHY v2.1 TX 2 trios/2 Lanes in TSMC (16nm, 12nm, N5)
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ROM Compiler IP, UMC 0.13um HS/FSG process
UMC 0.13um Logic HS FSG process Low Power synchronous VIA1 programmed ROM memory compiler.
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