RISC-V Platform-Level Interrupt Controller (PLIC) IP

IQonIC Works RISC-V PLIC IP is a platform-level interrupt controller conforming to the RISC-V PLIC specification, for use in systems with a large number of interrupt sources and multiple processor targets for interrupt delivery. It is configurable, and can be tailored to the number of sources and targets required by an application.

In a single-processor application, the PLIC connects to the AHB bus matrix and collects interrupt requests for AHB and APB I/O devices. The PLIC target interrupt requests connect to the RISC-V processor’s external interrupt request inputs, providing interrupts for machine-mode and user-mode contexts.

In a larger multiprocessor application, the PLIC connects to the shared AHB bus matrix and collects interrupt requests for AHB and APB I/O devices. The PLIC treats each execution context (machine mode, supervisor mode, user mode) on each processor as a separate target for interrupts. An interrupt can be enabled for multiple targets. The first processor to claim the interrupt by reading the corresponding PLIC claim register is responsible for handling the interrupt and for indication completion to the PLIC.

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