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RISC-V high performance CPU
Ventana's first generation RISC-V high performance CPU is targeted at data center, edge, and other general computing applications. The configurable CPU cluster can be integrated as IP within an SoC, delivered as an optimized compute chiplet, or within an ASSP/CSSP SiP standard product.
Veyron is a server-class CPU, meeting all the requirements to run virtualized cloud-native workloads and adhering to robust data center requirements. The V1 IP portfolio includes key RISC-V system IP components such as an IOMMU, and its interface is compliant to common AMBA protocol standards, such that complete high performance system solutions can be easily integrated with available third-party IP.
Veyron is a server-class CPU, meeting all the requirements to run virtualized cloud-native workloads and adhering to robust data center requirements. The V1 IP portfolio includes key RISC-V system IP components such as an IOMMU, and its interface is compliant to common AMBA protocol standards, such that complete high performance system solutions can be easily integrated with available third-party IP.
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Block Diagram of the RISC-V high performance CPU
RISC-V IP
- RISC-V ARC-V RMX-100 Ultra-low Power 32-bit Processor IP for Embedded Applications
- ARC-V RMX-500 power efficient 32-bit RISC-V processor for embedded applications
- ARC-V RHX-105 dual-issue, 32-bit RISC-V processor for real-time applications (multi-core)
- 32-bit Embedded RISC-V Functional Safety Processor
- 64-bit RISC-V Application Processor Core
- Dual-issue Linux-capable RISC-V core