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RISC-V debug solutions
RISC-V is a new open source instruction set architecture, initially developed by UC Berkeley but now being more widely adopted. As a member of the RISC-V Foundation, UltraSoC is a leading player in defining and implementing the debug architecture for RISC V standards.
Our RISC-V debug solution scales to suit any requirement. If you're developing a cost-sensitive uni-processor chip – for an IoT application, for example – you can use our IP to implement straightforward standards-compliant run-control and JTAG connectivity, supported by our Eclipse-based IDE. At the other end of the complexity spectrum, you can choose a system capable of delivering wire-speed trace and rich information about the operation of even the largest system-level SoC, with multiple CPUs.
Our RISC-V debug solution scales to suit any requirement. If you're developing a cost-sensitive uni-processor chip – for an IoT application, for example – you can use our IP to implement straightforward standards-compliant run-control and JTAG connectivity, supported by our Eclipse-based IDE. At the other end of the complexity spectrum, you can choose a system capable of delivering wire-speed trace and rich information about the operation of even the largest system-level SoC, with multiple CPUs.
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Block Diagram of the RISC-V debug solutions
RISC-V IP
- TESIC CC EAL5+ Secure Element IP Core
- RISC-V processor with vector extension certified for ISO 26262 ASIL D ready
- RISC-V 32bit CPU which supports ISO26262 ASIL D
- Intelligent Sensor and Power Management Design Platform
- Digital and mixed-signal IP and ASIC RISC-V reference design for USB Type-C/PD power adapter/charger
- Low-power 32-bit RISC-V processor