MIPI D-PHY Rx-Only 4 Lanes in TSMC (40nm, 28nm, 22nm, 16nm, 12nm, N7, N6)
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Register File with low power retention mode and 3 speed options
Low Leakage. Mobile Semiconductor's RF1P-ULL-GF22FDX memory compiler generates single-port Register File instances using the GLOBALFOUNDRIES 22nm FDX CMOS process. Each ultra-low leakage memory instance primarily uses low leakage HVT (LLHVT) devices and source biasing to minimize standby current. Read and write assist circuits ensure reliable operations with a periphery power supply as low as 0.72V.
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Single port register file IP
- Single Port Register File compiler - Memory optimized for high density and high speed - compiler range up to 40 k
- Single Port Register File compiler - Memory optimized for high density and high speed - compiler range up to 40 k
- Single Port Register File compiler - Memory optimized for high density and speed - Dual Voltage - compiler range up to 40 k
- Single Port Register File compiler - Memory optimized for ultra high density and high speed - compiler range up to 20 k
- Single Port Register File compiler - Memory optimized for ultra high density and high speed - compiler range up to 20 k
- Single Port Register File compiler - Memory optimized for high density and speed - Dual Voltage - Compiler range up to 40 kbits